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CML Semiconductor Products
PRODUCT INFORMATION
FX621
Features/Applications Meets 12kHz and 16kHz SPM Specifications Low-Power CMOS [ 3.5 - 5 Volt Operation ] Tone Follower and SPM Packet Detection Modes
Low-Power Subscriber Private Metering (SPM) Detector
Publication D/621/2 June 1991 Provisional Issue
Adjustable Input Gain PABX, Payphone and Telephone Applications General-Purpose Tone Detection Crystal Oscillator Stability
XTAL V DD
XTAL/CLOCK 4.433619 MHz OSCILLATOR
V SS 4.433619 MHz
V BIAS 3 or 4 AMP INPUT ( - ) - AMP INPUT (+) + 2 "SYSTEM GAIN SET" AMPLIFIER
1
SYSTEM SELECT 12/16 kHz
FREQUENCY DIVIDERS
1 MODE SELECT
FX621
AMP OUTPUT (GAIN SET)
554.203 kHz or 738.937 kHz LEVEL DETECTOR FREQUENCY WINDOW DETECTOR
OUTPUT RESET
DETECTOR INPUT
COUNTERS AND OUTPUT LOGIC OUTPUT
PULSE LENGTH TIME
SPACE LENGTH TIME
Fig.1 Internal Block Diagram
Brief Description
The FX621 is a single-chip, low-power CMOS tone detector designed for use in both PABX and general payphone applications for Subscriber Private Metering. The Decode and Not-Decode band edges are accurately defined by the use of an external 4.433619MHz crystal. Operation to either of the 12kHz or 16kHz SPM systems is pin programmable, with system amplitude sensitivities and pulse-length timing being provided by the use of external components. The FX621 has 2 pin-selectable modes of operation: 1) Tone Follower Mode. A logic "0" is output whenever a tone of the correct frequency and length is detected. 2) SPM Packet Mode. An output is obtained only when both the mark and space timing criteria of an input SPM tone have been fulfilled. The FX621, which is available in plastic DIL and SMD packages, requires only a single 3.5-volt (min.) power supply, a 4.433619MHz crystal with external gain and timing components to meet most SPM specifications.
Pin Number
DIL FX621P Quad FX621LG/LS
Function
1
1
Xtal/Clock: Input to the clock oscillator inverter. A single 4.433619MHz Xtal or external clock pulse input is required (see Figure 2). VDD: The positive supply rail. A single, stable supply in the range 3.5V to 5V is required. Detector Input: "Schmitt Trigger" level detector circuitry whose input thresholds are set internally and dependent on the applied VDD. For use with low signal-level systems this input should be preceded by the "System Gain Set" amplifier. To use this input without the "System Gain Set" amplifier, the components indicated in Figure 2 (inset) should be used with the protection diodes (D1 - D4). Amplifier Input (+): The positive and negative inputs to the "System Gain Set" Amplifier. With single or differential inputs this amplifier and its external circuitry can be used to provide the extra gain required to set the device to the user's National Level Specification. External diodes are used at both inputs (if in use) to provide protection when the line input level exceeds the supply rails (above the Absolute Maximum Rating). If this device is used without this amplifier, the protection diodes should be employed at the Detector Input. See Figure 2.
2 3
2 5
4
6
5
7
Amplifier Input (-):
6
8
Amplifier Output: The output of the "System Gain Set" Amplifier, is used with gain setting components. See Figures 1 and 2. VSS: The negative supply rail, (GND). VBIAS: The internal analogue bias pin, this point is at VDD/2 and requires to be externally decoupled to VSS via capacitor C3. Space Length Time: Active only in the `SPM Packet' mode, this input, with an external RC network, sets the minimum valid No-Tone (Space) period for the incoming packet using the formula: tS = 0.7 (R6 x C5). If the `SPM Packet' mode is not required these timing components may be omitted. See Page 4. Pulse Length Time: Active only in the `SPM Packet' mode, this input, with an external RC network, sets the minimum valid Tone period for the incoming packet using the formula: tM = 0.7 (R5 x C4). If the `SPM Packet' mode is not required these timing components may be omitted. See Page 4. Output Reset: This input is used only in the `SPM Packet' mode. Once an SPM packet has been detected and an output generated (logic "0") from this device the output remains as set until this input is strobed to a logic "0." See Figure 3. This input has an internal 1M pullup resistor. Mode Select: A control pin to select either the `Tone Follower' mode or the `SPM Packet' mode. A logic "1" selects `Tone Follower', a logic "0" selects `SPM Packet.' This input has an internal 1M pullup resistor (Tone Follower). Output: The digital output of the SPM Detector. In the `Tone Follower' mode a valid tone gives a logic "0" and no-tone gives a logic "1." Tonebursts and tone dropouts of less than 16 cycles are ignored. In the `SPM Packet' mode the output is set to a logic "0" when a valid `packet' is measured. The output remains as set until reset by a logic "0" at the Output Reset function, see Figure 3. System Select: A control pin to set the device to work on either a 12kHz (logic "1") or 16kHz (logic "0") SPM system. This input has an internal 1M pullup resistor (12kHz). Xtal: The output of the clock oscillator inverter, see Figure 2.
8 9
12 13
10
14
11
17
12
18
13
19
14
20
15
23
16
24 3, 4, 9, 10, 11, 15, 16, 21, 22.
7
No internal connection - leave open circuit.
2
Application Information
The notes on these pages are intended to assist in calculating the external components required to operate the FX621 as an SPM Detector.
DETECTOR INPUT
FX621P PIN No.
VDD X1 XTAL/CLOCK V BIAS
D1 D2
3 C9 R7
XTAL 16 15 14
R5
R6
VBIAS
INSET
1 V DD DETECTOR INPUT AMP INPUT (+) AMP INPUT (-) 2 3 4 5 6 7 8
R4 C8
SYSTEM SELECT OUTPUT MODE SELECT OUTPUT RESET PULSE LENGTH SPACE LENGTH
C6
C1
R1
FX621P
13 12 11 10 9
C2
R2
R3
AMP OUTPUT
x
C7 D3 D4
V SS
V BIAS
C3 C4 C5
V BIAS V SS
(a) Differential Input Configuration
Component References
Component Reference Component R1 Note 4 C1 R2 Note 4 C2 R3 390k 1.0% C3 R4 390k 1.0% C4 R5 Note 5 C5 R6 Note 5 C6 R7 1.0M C7 D1 to D4 1N4148 or equivalent C8 (small signal type) C9 X1 4.433619MHz Reference Note 4 Note 4 1.0F 20% Note 5 Note 5 1.0F 20% 12.0pF 10.0% 12.0pF 10.0% 0.1F 10.0%
V BIAS
C7
D1 5 C2 R2 D3 4
R3
"SYSTEM GAIN SET" AMPLIFIER
6
3
+
C3
AMP DETECTOR OUTPUT INPUT
V BIAS V SS
(b) Single Input Configuration
Fig.2 Recommended External Components
Gain Component Calculations
(1)
Calculate the FX621 sensitivity.
Device Sensitivity - at the Detector Input (Figure 1) is dependent upon the VDD value and is calculated as: Device Sensitivity 0.2 x VDD 2 x 2
(4) Calculate the gain/attenuation components for the chosen gain.
Gain Components - for a differential input: R1 = R2 R3 = R4 Gain = ZFeedback ZInput C8 = C7 C1 = C2 (R4 //X(C8)) (R1 + X(C1))
(Vrms)
(2) Ascertain the required National {Minimum WillDecode} and [Maximum Will-Not Decode] Levels. (3) Calculate the acceptable range of required Gain/ Attenuation for the levels in Note 2, using the "System Gain Set" amplifier.
The gain requirement is calculated as : [Max] / {Min} Gain = Device Sensitivity { Minimum Will-Decode Level } [ Maximum Will-Not Decode Level ]
This calculation approximates as:
R1 R4 1.2 x (selected gain) and C1 1 2 x R1 x 6.0kHz - using the nearest preferred value components. The values of R1 and C1 have been calculated to give a highpass cut-off between the audio and SPM tone frequencies, approximately 6kHz. C7 and C8 are anti-alias components and are calculated for an approximate cut-off frequency of 32kHz.
[or]
Choose a gain figure that meets both level requirements.
3
Application Information ......
(5)
Timing Components
(6)
Protection Diodes
In the `SPM Packet' mode R5 and C4 set the minimum 'Tone' period (tM), R6 and C5 set the minimum 'Space' period (tS), and are calculated as follows: tM = 0.7(R5 x C4). tS = 0.7(R6 x C5).
As most telephone systems operate at voltages in excess of the Absolute Maximum Limits for damage, diodes D1 - D4 are essential for device protection.
When calculating Tone and Space time settings the following points should be taken into consideration: (7) (1) (2) (3) Response and De-response times tR and tD. Component tolerances can alter the calculation. The MINIMUM expected pulse/space length must be catered for.
Component Tolerances The tolerances of external components used with this device are dependent upon the required accuracy of the gain and pulse period timings.
Timing
Figure 3 shows the FX621 output timing - Timing value limits are given on the "Specification" page.
Note - There is no reaction to pulses or drop-outs of less than the valid Response or De-response time.
TONE FOLLOWER MODE
TONE INPUT
tR
OUTPUT
tD
NOTE
tR
NOTE
tD
SPM PACKET MODE
TONE INPUT
tR tM
OUTPUT
tD tS
tR
OUTPUT RESET
t RESET
Fig.3 Output Timing
Example Values
- for the FX621 to operate with the West German (16kHz) 'FTZ' Specification.
= = = = 71.3 mV rms 10.0 V rms 34.6 mVrms 248.0 mVrms 3.47 7.17 4.7 For a chosen gain figure of 4.7, a minimum Tone length of 80ms, a minimum Space length of 135ms and a VDD of 3.5V, the required component values are : R1 R2 R3 R4 R5 R6 X1 Tolerances: 68k 68k 390k 390k 100k 120k 4.433619MHz C1 C2 C3 C4 C5 C6 C7 C8 330pF 330pF 1.0F 820nF 1.0F 1.0F 12pF 12pF
(a) Min. 'Will Decode' Level (b) Max. 'Will Decode' Level (c) Max. 'Will-Not Decode' Level (d) Device Sensitivity @ 3.5V VDD Min. Gain Required Max. Gain Allowed Chosen Gain Figure
(d/a) (d/c)
Resistors = 1%. Capacitors = 10%.
4
Specification
Absolute Maximum Ratings
Exceeding the maximum rating can result in device damage. Operation of the device outside the operating limits is not implied. Supply Voltage Input Voltage at any pin (ref VSS = 0V) Sink/source current (supply pins) (other pins) Total device dissipation @ TAMB 25C Derating Operating temperature range: Storage temperature range: FX621P/LG/LS FX621P/LG/LS -0.3 to 7.0V -0.3 to (VDD + 0.3V) 30mA 20mA 800mW Max. 10mW/C -30C to + 70C -40C to + 85C
Operating Limits
All device characteristics are measured under the following conditions unless otherwise specified : VDD = 3.5V TAMB = 25C Xtal/Clock fC = 4.433619MHz Audio level 0dB ref = 775mV rms
Characteristics
Static Values Supply Voltage (VDD) Supply Current (IDD) Input Logic "1" Input Logic "0" Output Logic "1" Output Logic "0" Impedances "Gain Set" Amplifier Input "Gain Set" Amplifier Output Analogue Detector Input Digital Inputs Digital Output Dynamic Values Sensitivity Required Signal to Noise Ratio Upper Detector Threshold Lower Detector Threshold Amplifier Input Offset Xtal Oscillator Frequency Frequency Discrimination 'Will-Decode' Frequency Limits 'Will-Not Decode' Frequency Limits
System See Note
Min.
3.5 - 70.0 0 80.0 - 1.0 - 1.0 0.5 -
Typ.
- 1.0 - - - - - - - 1.0 - 248 45.0 2.1 1.4 15.0 4.433619 - - - - - - - - 1.7 1.2 1.7 1.2 -
Max.
5.0 1.4 100 30.0 - 20.0 - 10.0 - - 10.0 - - 2.14 1.44 -
Unit
V mA % VDD % VDD % VDD % VDD M k M M k mVrms dB V V mV MHz kHz kHz kHz kHz kHz kHz cycles ms ms ms ms ms ns
12kHz/16kHz
1, 2 7 2 2
- - 2.06 1.36 -
12kHz 16kHz 12kHz 12kHz 16kHz 16kHz 12/16kHz 12/16kHz 12kHz 16kHz 12kHz 16kHz 12/16kHz 3, 4 4 5, 7 5, 7 6, 7 6, 7 4
11.82 15.76 0 12.48 0 16.64 16.0 5.0 - - - - 150.0
12.18 16.24 11.52 - 15.36 - - - 3.0 2.0 3.0 2.0 -
Timing Information - Fig.3 Valid Tone Burst Length (tM) Valid Space Length (tS) Tone Response Time (tR) De-response Time (tD) SPM Output Reset Time (tRESET) Notes 1. 2. 3. 4.
Device sensitivity at the Detector Input pin, or using the 'Gain Set' Amplifier at unity. These values are quoted at 3.5 volt VDD, any supply variation will alter levels accordingly. Tone Follower mode. SPM Packet mode, in this mode the minimum valid Pulse (Space) length is programmable by means of an RC network on the Pulse (Space) Length Time pin. If no RC network is used, the minimum valid tone length reverts to 16 cycles. 5. The time for the circuit to recognize a valid 'Tone' in the Tone Follower mode. 6. The time for the circuit to recognize a valid 'No Tone' in the Tone Follower mode. 7. The FX621 is a low-power zero crossing detector without on-chip filtering, for use with a good Signal-to-Noise ratio. The FX611 is recommended for high noise environments. If the supply current requirement of the FX611 is unacceptable, separate external filters should be employed with the FX621.
5
Package Outlines
The FX621 is available in the package styles outlined below. Mechanical package diagrams and specifications are detailed in Section 10 of this document. Pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top.
Handling Precautions
The FX621 is a CMOS LSI circuit which includes input protection. However precautions should be taken to prevent static discharges which may cause damage.
FX621P 16-pin DIL Package
FX621LG 24-pin Package
NOT TO SCALE
NOT TO SCALE
Max. Body Length Max. Body Width
10.49mm 7.59mm
Max. Body Length Max. Body Width
10.25mm 10.25mm
FX621LS 24-lead Package
Ordering Information FX621P FX621LG 16-pin plastic DIL 24-pin quad plastic encapsulated bent and cropped 24-lead plastic leaded chip carrier
NOT TO SCALE
FX621LS
Max. Body Length Max. Body Width
10.40mm 10.40mm
CML does not assume any responsibility for the use of any circuitry described. No circuit patent licences are implied and CML reserves the right at any time without notice to change the said circuitry.
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
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Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
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D/CML (D)/1 February 2002

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